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1 of 23 optimum technology matching? applied gaas hbt ingap hbt gaas mesfet sige bicmos si bicmos sige hbt gaas phemt si cmos si bjt gan hemt functional block diagram rf micro devices?, rfmd?, optimum technology matching?, enabling wireless connectivity?, powerstar?, polaris? total radio? and ultimateblue? are trademarks of rfmd, llc. bluetooth is a trade- mark owned by bluetooth sig, inc., u.s.a. and licensed for use by rfmd. all other trade names, trademarks and registered tradem arks are the property of their respective owners. ?2006, rf micro devices, inc. product description 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . bifet hbt ldmos ? synth phase det. ref. divider rffc2071 synth phase det. ref. divider rffc2072 rffc2071/2072 2.7ghz rf synthesizer/vco with integrated rf mixer the rffc2071 and rffc2072 are re-configurable frequency conversion devices with integrated fractional-n phased locked loop (pll) synthesizer, voltage con- trolled oscillator (vco) and either one or two high linearity mixers. the fractional-n synthesizer takes advantage of an advanced sigma-delta modulator that delivers ultra-fine step sizes and low spurious pr oducts. the pll/vco engine combined with an external loop filter allows the user to generate local oscillator (lo) signals from 85mhz to 2700mhz. the lo signal is buffered and routed to the integrated rf mix- ers which are used to up/down-convert frequencies ranging from 30mhz to 2700mhz. the mixer bias current is prog rammable and can be reduced for applica- tions requiring lower power consumption. both devices can be configured to work as signal sources by bypassing the integrated mixers. device programming is achieved via a simple 3-wire serial interface. in addition, a unique programming mode allows up to four devices to be controlled from a common serial bus. this eliminates the need for separate chip-sel ect control lines between each device and the host controller. up to six general purpose outputs are provided, which can be used to access internal signals (e.g. the lo ck signal) or to control front end compo- nents. both devices operate with a 2.7v to 3.3v power supply. features ? 85mhz to 2700mhz lo frequency range ? fractional-n synthesizer with very low spurious levels ? typical step size 1.5hz ? fully integrated low phase noise vco and lo buffers ? integrated phase noise 0.18rms at 1ghz ? high linearity rf mixer(s) ? 30mhz to 2700mhz mixer frequency range ? input ip3 +23dbm ? mixer bias adjustable for low power operation ? full duplex mode (rffc2071) ? 2.7v to 3.3v power supply ? low current consumption ? 3- or 4-wire serial interface applications ? catv head-ends ? digital tv repeaters ? multi-dwelling units ? diversity receivers ? software defined radios ? frequency band shifters ? point-to-point radios ? cellular repeaters ? wimax/lte infrastructure ? cellular jammers ? satellite communications ? vhf/uhf radios ds100920 package: qfn, 32-pin, 5mmx5mm rffc2071/20 72 2.7ghz rf synthe- sizer/vco with integrated rf mixer
2 of 23 rffc2071/2072 ds100920 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . absolute maximum ratings parameter rating unit supply voltage (v dd ) -0.5 to +3.6 v input voltage (v in ) any pin -0.3 to v dd +0.3 v rf/if mixer input power +15 dbm operating temperature range -40 to +85 c storage temperature range -40 to +150 c parameter specification unit condition min. typ. max. esd requirementsl human body model 2000 v general 1000 v rf pins machine model 200 v general 100 v rf pins operating conditions supply voltage (v dd ) 2.7 3.0 3.3 v temperature (t op )-40 +85c logic inputs/outputs ( v dd =supply to dig_vdd pin) input low voltage -0.3 +0.5 v input high voltage 1.5 v dd v input low current -10 +10 ua input=0v input high current -10 +10 ua input=v dd output low voltage 0 0.2*v dd v output high voltage 0.8*v dd v dd v load resistance 10 k ? load capacitance 20 pf gpo drive capability sink current 20 ma at v ol =0.6v source current 20 ma at v ol =2.4v output impedance 25 static supply current (i dd ) with 1ghz lo 100 ma low current, mix_idd=1, one mixer enabled. 125 ma high linearity, mix_idd=6, one mixer enabled. standby 2 ma reference oscillator and bandgap only. power down current 300 ua enbl=0 and ref_stby=0 mixer 1/2 (mixer output driving 4:1 balun) gain -2 db not including balun losses noise figure 10 db low current setting 13 db high linearity setting iip3 +10 dbm low current setting +23 dbm high linearity setting input port frequency range 30 2700 mhz mixer input return loss 10 db 100 ? differential output port frequency range 30 2700 mhz caution! esd sensitive device. exceeding any one or a combination of the absolute maximum rating conditions may cause permanent damage to the device. extended application of absolute maximum rating conditions to the device may reduce device reliability. specified typical perfor- mance or functional operation of the devi ce under absolute maximum rating condi- tions is not implied. rohs status based on eudirective2002/95/ec (at time of this document revision). the information in this publication is believed to be accurate and reliable. however, no responsibility is assumed by rf micro devices, inc. ("rfmd") for its use, nor for any infringement of patents, or other rights of third parties, resulting from its use. no license is granted by implication or otherwise under any patent or patent rights of rfmd. rfmd reserves the right to change component circuitry, recommended appli- cation circuitry and specifications at any time without prior notice.
3 of 23 rffc2071/2072 ds100920 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . parameter specification unit condition min. typ. max. reference oscillator external reference frequency 10 104 mhz reference divider ratio 1 7 external reference input level 500 800 1500 mvp-p ac-coupled synthesizer (loop ba ndwidth of 200khz, 52mhz reference) synthesizer output frequency 85 2700 mhz phase detector frequency 52 mhz phase noise (lo=1ghz) -108 dbc/hz 10khz offset -108 dbc/hz 100khz offset -135 dbc/hz 1mhz offset 0.19 rms integrated from 1khz to 40mhz phase noise (lo=2ghz) -102 dbc/hz 10khz offset -102 dbc/hz 100khz offset -130 dbc/hz 1mhz offset 0.32 rms integrated from 1khz to 40mhz normalized phase noise floor -214 dbc/hz measured at 20khz to 30khz offset voltage controlled oscillator open loop phase noise at 1mhz offset 2.5ghz lo frequency -134 dbc/hz vco3 2.0ghz lo frequency -135 dbc/hz vco2 1.5ghz lo frequency -136 dbc/hz vco1 open loop phase noise at 10mhz offset 2.5ghz lo frequency -149 dbc/hz vco3 2.0ghz lo frequency -150 dbc/hz vco2 1.5ghz lo frequency -151 dbc/hz vco1
4 of 23 rffc2071/2072 ds100920 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . note 1: an rc low pass filter could be used on this line to reduce digital noise. note 2: if the device is under software control this in put can be configured as a general purpose output (gpo). note 3: connect a 51k ? resistor from this pin to ground, this pin is sensitive to low frequency noise injection. note 4: dc voltage should not be applied to this pin. use eith er an ac-coupling capacitor as part of lumped element matching network or a transformer (see evaluation board schematic). note 5: this pin must be connected to ana_vdd2 using an rf choke or a transformer (see application schematic). pin function description 1enbl/gpo5 device enable pin. see note 1 and 2. 2ext_lo external local oscillator input. 3ext_lo_dec decoupling pin for external local oscillator. 4rext external bandgap bias resistor. see note 3. 5ana_vdd1 analog supply. use good rf decoupling. 6lfilt1 phase detector output. low-frequency noise-sensitive node. 7lfilt2 loop filter op-amp output. low-frequency noise-sensitive node. 8lfilt3 vco control input. low-frequency noise-sensitive node. 9 mode/gpo6 mode select pin. see note 1 and 2. 10 ref_in reference input. use ac coupling capacitor. 11 nc 12 tm connect to ground. 13 mix1_ipn differential input 1 (see note 4). on rffc2072 this pin is nc. 14 mix1_ipp differential input 1 (see note 4). on rffc2072 this pin is nc. 15 gpo1/add1 general purpose output / multislice address bit. 16 gpo2/add2 general purpose output / multislice address bit. 17 mix1_opn differential output 1 (see note 5). on rffc2072 this pin is nc. 18 mix1_opp differential output 1 (see note 5). on rffc2072 this pin is nc. 19 dig_vdd digital supply. should be decoupled as close to the pin as possible. 20 nc 21 nc 22 ana_vdd2 analog supply. use good rf decoupling. 23 mix2_ipp differential input 2 (see note 4). 24 mix2_ipn differential input 2 (see note 4). 25 gpo3/fm general purpose output / frequency control input. 26 gpo4/ld/do general purpose output / lock detect output / serial data out. 27 mix2_opn differential output 2 (see note 5). 28 mix2_opp differential output 2 (see note 5). 29 resetx chip reset (active low). connect to dig_vdd if asynchronous reset is not required. 30 enx serial interface select (active low). see note 1. 31 sclk serial interface clock. see note 1. 32 sdata serial interface data. see note 1. exposed paddle ground reference, should be connected to pcb ground through a low impedance path.
5 of 23 rffc2071/2072 ds100920 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . theory of operation the rffc2071 and rffc2072 are wideband rf frequency converte r chips which include a fractional-n synthesizer and a low noise vco core. the rffc2071 has an lo si gnal multiplexer, two lo buffer circuits, and two rf mixers. the rffc2072 has a single lo buffer circuit and one rf mixer. both devices have an integrated voltage reference and low drop out regulators sup- plying critical circuit blocks such as the vcos and synthesize r. synthesizer programming, device configuration and control are achieved through a mixture of hardware and software controls . all on-chip registers are programmed through a simple 3-wire serial interface. vco the vco core in the rffc2071 and rffc2072 consists of three vc os which, in conjunction with the integrated lo dividers of /2 to /32, cover the lo range of 85mhz to 2700mhz. each vco has 128 overlapping bands which are used to achieve low vco gain and optimal phase noise performance across the whole tu ning range. the chip automatically selects the correct vco (vco auto-select) and vco band (vco coarse tuning) to genera te the desired lo frequency based on the values programmed into the pll1 and pll2 registers banks. the vco auto-select and vco coarse tuning are triggered every time enbl is taken high, or if the pll re-lock self clearing bit is programmed high. once the correct vco and band have been select ed the pll will lock onto the correct frequency. during the band selection process, fixed capacitance elements are progressively connected to the vco resonant circuit until the vco is oscillating approximately at the correct frequency. the output of this band selection, ct_cal, is made available in the read- back register. a value of 127 or 0 in this register indicates th at the coarse tuning was unsucc essful, and this will also be in di- cated by the ct_failed flag also availabl e in the read-back register. a ct_cal value between 1 and 126 indicates a success- ful calibration, the actual value being dependent on the desire d frequency as well as process variation for a particular device . the band select process will center the vco tuning voltage at about 1.0v, compensating for manufacturing tolerances and pro- cess variation as well as environmental factors including temperat ure. in applications where the device is left enabled at the same lo frequency for some time, it is recommended that aut omatic band selection be performed for every 30c change in temperature. this assumes an active loop filter. the rffc2071 and rffc2072 feature a differential lo input to a llow the mixer to be driven from an external lo source. the fractional-n pll can be used with an external vco driven into this lo input, which may be useful to reduce phase noise in some applications. this may also require an external op-amp, dependant on the tuning voltage required by the external vco. in the rffc2071 the lo signal is routed to mixer 1, mixer 2, or both mixers depending on the state of the mode pin (or mode bit if under software control) and the value of the fulld bit. se tting fulld high puts the device into full duplex mode and bot h mixers are enabled. fractional-n pll the rffc2071 and rffc2072 contain a charge pump-based fractional-n phase locked loop (pll) for controlling the three vcos. the pll includes automatic calibration systems to coun teract the effects of process and environmental variations, ensuring repeatable loop response and phase noise performance. as well as the vco auto-select and coarse tuning, there is a loop filter calibration mechanism which can be enabled if requ ired. this operates by adjusting the charge pump current to maintain loop bandwidth. this can be useful for applicat ions where the lo is tuned over a wide frequency range. the pll has been designed to use a reference frequency of between 10mhz and 104mhz from an external source, which is typically a temperature controlled crystal oscillator (tcxo). a refe rence divider (divide by 1 to divide by 7) is supplied and should be programmed to limit the frequency at the phase detector to a maximum of 52mhz. two pll programming banks are provided, the first bank is preceded by the label pll1 and the second bank is preceded by the label pll2. for the rffc2071 these banks are used to program mixer 1 and mixer 2 respectively, and are selected automati- cally as the mixer is selected using mode. for the rffc20 72 mixer 2 and register bank pll2 are normally used. the vco outputs are first divided down, typically by two, in a hi gh frequency prescalar. the output of this high frequency pres - calar then enters the n divider, which is a fractional divide r containing a dual-modulus prescaler and a digitally spur-compen-
6 of 23 rffc2071/2072 ds100920 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . sated fractional sequence generator. this allows very fine frequency steps and minimizes fractional spurs. the fractional energy is randomized and appears as frac tional noise at frequency offsets above 100k hz which will be attenuated by the loop filter. an external loop filter is used, giving flexibility in setting loop bandwidth for optimizing phase noise and lock time, for example. the synthesizer step size is typically 1.5hz when using a 26mh z reference frequency. the exact step size for any reference and lo frequency can be calculated using the following formula: (f ref * p) / (r * 2 24 * lo_div) where f ref is the reference frequency, r is the reference division ra tio, p is the prescalar division ratio, and lo_div is the lo divider value. pin 26 (gpo4) can be configured as a lock detect pin. the lock status is also available in the read-back register. the lock det ect function is a window detector on the vco tuning voltage. the lock flag will be high to show pll lock which corresponds to the vco tuning voltage being within the specified range, typically 0.30v to 1.25v. the lock time of the pll will depend on a number of factors; including the loop bandwidth and the reference frequency at the phase detector. this clock frequency determines the speed at wh ich the state machine and internal calibrations run. a 52mhz phase detector frequency will give fastest lock times, of typically 40usecs when using the pll re-lock bit. phase detector and charge pump the phase detector provides a current output to drive an extern al loop filter. an on-chip operational amplifier can be used to design an active loop filter, or a passive design can be implem ented. the charge pump output current is set by the value con- tained in the p1_cp_def an d p2_cp_def fields in the loop filter configurat ion register. the charge pump current is given by approximately 3ua/bit, and the fields are 6 bits long. this gives default value (31) of 93ua and maximum value (63) of 189ua. if the automatic loop bandwidth calibratio n is enabled the charge pump current is set by the calibration algorithm based upon the vco gain. the phase detector will operate with a maximum input frequency of 52mhz. loop filter the pll may be designed to use an active or passive loop filter as required. the internal configuration of the chip is shown below with the recommended active loop filter. if the lf_act bit in the loop filter configuration register is asserted high, th en the op-amp will be enabled. if the lf_act bit is asserted low, the internal op-amp is disabled and a high impedance is pre- sented to the lfilt1 pin. the phase detector polarity is also automatically inverted when lf_act is low, since with a passive loop filter there is no inversion in the op-amp. lfilt1 8p2 180p 22k 470r 470r 330p 330p lfilt2 lfilt3 +1.1v
7 of 23 rffc2071/2072 ds100920 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . the charge pump output voltage compliance range is typically +0 .7v to +1.5v. for applications using a passive loop filter, vco coarse tuning must be performed regularly enough to ensure that the vco tuning voltage falls within this compliance range at all temperatures. the active loop filter automatically maintains the charge pump output voltage in the center of the compliance range, and the op-amp provides a wider vco tu ning voltage range, typically 0v to +2.4v. external reference the rffc2071 and rffc2072 have been designed to use an exte rnal reference such as a tcxo. the typical input will be a 0.8vp-p clipped sine wave, which should be ac-coupled into the reference input. when the pll is not in use, it may be desir- able to turn off the internal reference circuits, by setting the refstby bit low, to minimize current draw while in standby mod e. on cold start, or if refstby is programmed low, the reference circuits will need a warm-up period. this is set by the su_wait bits. this will allow the clock to be stable and immediately avai lable when the enbl bit is asserted high, allowing the pll to assume normal operation. if the current consumption of the reference circuits in standby mode, typically 2ma, is not critical, then the refstby bit can be set high. this allows the fastest startup and lock time after enbl is taken high. wideband mixer the mixers are wideband, double-balanced gilbert cells. they support rf/if frequencies from 30mhz up to 2700mhz. each mixer has an input port and an output port that can be used for either if or rf (in other words, for up- or down-conversion). t he mixer current can be programmed to between about 15ma and 45ma depending on line arity requirements. the majority of the mixer current is sourced through the output pins via either a ce nter-tapped balun or an rf choke in the external matching cir- cuitry to the supply. the rf mixer input and output ports are differential and require baluns and simple matching circuits optimized to the specific application frequencies. a conversion gain of approximatel y -2db (not including balun losses) is achieved with 100 differen- tial input impedance, an d the outputs driving 200 differential load impedance. increa sing the mixer output load increases the conversion gain. the mixer has a broadband common gate input. the input impeda nce is dominated by the resistance set by the mixer 1/gm term, which is inversely proportional to the mixer cu rrent setting. the resistance will be approximately 85 at the default mixer current setting (100). there is also some shunt capacitance at the mixer input, and the inductance of the bond wires (about 0.5nh on each pin) to consider at higher frequencies. the fo llowing diagram is a simple model of the mixer input impedance: the mixer output is high impedance, consisting of approximately 2k resistance in parallel with some capacitance, approxi- mately 1pf. the mixer output does not require a conjugate matching network. it is a constant current output which will drive a real differential load of between 50 ? and 500 ? , typically 200 ? . since the mixer output is a constant current source, a higher resistance load will give higher output voltage and gain. a shunt inductor can be used to resonate with the mixer output capac- itance at the frequency of interest. this inductor may not be required at lower frequencies where the impedance of the output rffc207x mixer input 0.5nh 0.5nh rin typ 85 0.5pf
8 of 23 rffc2071/2072 ds100920 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . capacitance is less significant. at higher output frequencies the inductance of the bond wires (about 0.5nh on each pin) becomes more significant. the following diagram is a simple model of the mixer output: the rffc2071 mixer layout and pin placemen t has been optimized for high mixer-to-mixer isolation of greater than 60db. the mixers can be set up to operate in half duplex mode (1 mixer ac tive) or full duplex mode (both mixers active). this selection i s done via control of mode and by setting the fulld bit. when in full duplex mode, either pll register bank can be used, the lo signal is routed to both mixers. serial interface all on-chip registers in the rffc2071 and rffc2072 are programmed using a proprietary 3-wire serial bus which supports both write and read operations. synthesizer programming, device configuration, and control are achieved through a mixture of hardware and software controls. certain functions and operatio ns require the use of hardware controls via the enbl, mode, and resetb pins in addition to programming via the serial bus. alternatively there is the option to control the chip completely via the serial bus. the serial data interface can be configured for 4-wire operation by setting the 4wire bit in the sdi_ctrl register high. then p in 26 is used as the data out pin, and pin 32 is the serial data in pin. hardware control three hardware control pins are provided: enbl, mode, and resetb. the enbl pin has two functions: to enable the analog circuits in the chip and to trigger the vco auto-selection and coarse tun- ing mechanisms. the vco auto-selection and coarse tuning is initiated when the enbl pin is taken high. every time the fre- quency of the synthesizer is reprogrammed, enbl has to be assert ed high to initiate these mechanisms and then to initiate the pll locking. alternatively following the programming of a new frequency the pll re-lock self clearing bit could be used. if the device is left in the enabled state for long periods, it is recommended that vco auto-se lection and coarse tuning (band selection) is performed for every 30c change in temperature. th e lock detect flag can be used to indicate when to perform the vco calibration, it shows that the vco tuning volt age has drifted significantly with changing temperature. the resetb pin is a hardware reset control that will reset all digital circuits to their startup state when asserted low. the d evice includes a power-on-reset function, so this pin should not normally be required, in which case it should be connected to the positive supply. the mode pin controls which mixer(s) and pll programming register bank is active. mode fulld active pll register bank active mixer low 0 1 1 high 0 2 2 low 1 1 1 and 2 high 1 2 1 and 2 rffc207x mixer output 0.5nh 0.5nh 1k 1pf 1k
9 of 23 rffc2071/2072 ds100920 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . serial data interface control the normal mode of operation uses the 3-wire serial data inte rface to program the device registers, and three extra hardware control lines: mode, enbl and resetb. when the device is under software control, achieved by settin g the sipin bit in the sdi_ctrl register high, then the hardware can be controlled via the sdi_ctrl register. when this is the case, the three hardware control lines are not required. if the device is under software control, pins 1 and 9 ca n be configured as general purpose outputs (gpo). multi-slice mode the multi-slice mode of operation allows up to four chips to be controlled from a common serial bus. the device address pins a0 and a1 are used to set the address of each part. on power up, and after a reset, the devices ignore the address pins (a1 and a2, pins 15 and 16) and any data presented to the serial bus will be programmed into all the devices. however, once the sipin bit in the sdi_ctrl register is set, each device th en adopts an address according to the state of the address pins on the device. general purpose outputs the general purpose outputs (gpos) can be controlled via the gpo register and will depend on the state of mode since they can be set in different states corresponding to either mixer path 1 or 2. for example, the gpos can be used to drive leds or to control external circuitry such as switches or low power lnas. each gpo pin can supply approximately 20ma load current. the outp ut voltage of the gpo high state will drop with increased current drive by approximately 25mv/ma. similarly the output voltage of the gpo low state will rise with increased current, again by approximately 25mv/ma. external modulation the rffc2071 and rffc2072 fractional-n synthesizer can be used to modulate the frequency of the vco. there are two dedi- cated registers, ext_mod and fmod, which can be used to configur e the device as a modulator. it is possible to modulate the vco in two ways: 1.binary fsk the modsetup bits in the ext_mod register are set to 11. gpo3 is then configured as an input and used to control the signal frequency. the frequency deviation is set by the modstep and modulation bits in the ext_mod and fmod registers respec- tively. the modulation frequency is calculated according to the following formula: slice2 (0) slice2 (1) slice2 (2) slice2 (3) a1 a2 enx sdata sclk vdd vdd vdd vdd a1 a2 a1 a2 a1 a2
10 of 23 rffc2071/2072 ds100920 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . where modulation is a 2's complement number and f pd is the phase detector frequency. 2.continuous modulation the modsetup bits in the ext_mod register are set to 01. the frequency deviation is set by the modstep and modulation bits in the ext_mod and fmod registers respectively. the vco fr equency is then changed by writing a new value into the mod- ulation bits, the vco frequency is instantly updated. an arbi trary frequency modulation can then be performed dependant only on the rate at which values are written into the fmod register. the modulation frequency is calculated according to the following formula: where modulation is a 2's complement number and f pd is the phase detector frequency. programming information the rffc2071 and rffc2072 share a common serial interface and control block. please refer to the following documents for further details on programming and control: ? slice2 register map and programming guide ? slice2 mixer programming guide these documents are available for download fr om http://rfmd.com/products/intsynthmixer/. evaluation boards evaluation boards for rffc2071 and rffc2072 are provided as part of a design kit, along with the necessary cables and pro- gramming software tool to enable full evaluation of the device . the evaluation board has been configured for wideband opera- tion. the mixer inputs and outputs are connected to wideband transmission line transformer baluns. design kits can be ordered from www.rfmd.com or from local rfmd sales offices and authorized sales channels. fo r ordering codes please see ?ordering information? on page 23. for further details on how to set up the design kits please refer the following document: ? slice2 evaluation board and gui user guide these documents are available for download fr om http://rfmd.com/products/intsynthmixer/ f mod 2 modstep f pd modulation () 2 16 ? ?? = f mod 2 modstep f pd modulation () 2 16 ? ?? =
11 of 23 rffc2071/2072 ds100920 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . detailed functional block diagram pre- scaler mux /2 n [n=1..5] n divider sequence generator phase detector reference divider charge pump gpo control biasing & ldos lock flag xo ext lo 51k +3v mode enbl reset enx sdata sclk rfxf8553 4:1 balun +3v op1 rfxf8553 4:1 balun +3v op2 rfxf9503 1:1 balun ip2 rfxf9503 1:1 balun ip1 loop filter 3-wire serial bus control lines mixer 2 mixer 1 rffc2071 only
12 of 23 rffc2071/2072 ds100920 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . rffc2071 pin out rffc2072 pin out 1 2 3 4 5 6 7 8 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 exposed paddle enbl/gpo5 ext_lo ext_lo_dec rext ana_vdd1 lfilt1 lfilt2 lfilt3 gpo2/add2 gpo1/add1 mix1_ipp mix1_ipn tm xtaln xtalp mode/gpo6 gpo3/fm gpo4/ld/do mix2_opn mix2_opp resetx enx sclk sdata mix2_ipn mix2_ipp ana_vdd2 nc nc dig_vdd mix1_opp mix1_opn 1 2 3 4 5 6 7 8 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 24 23 22 21 20 19 18 17 exposed paddle enbl/gpo5 ext_lo ext_lo_dec rext ana_vdd1 lfilt1 lfilt2 lfilt3 gpo2/add2 gpo1/add1 tm xtaln xtalp mode/gpo6 gpo3/fm gpo4/ld/do mix_opn mix_opp resetx enx sclk sdata mix_ipn mix_ipp ana_vdd2 nc nc dig_vdd nc nc nc nc
13 of 23 rffc2071/2072 ds100920 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . application schematic
14 of 23 rffc2071/2072 ds100920 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . typical synthesizer performance characteristics v dd =+3v and ta=+27c unless stated. measured on rffc2071/rffc2072 evaluation board with active loop filter. -160.0 -150.0 -140.0 -130.0 -120.0 -110.0 -100.0 -90.0 -80.0 -70.0 -60.0 1.0 10.0 100.0 1000.0 10000.0 100000.0 phase noise (dbc/hz) offset frequency (khz) synthesizer phase noise 4000mhz vco frequency, 26mhz crystal oscillator 2000mhz 1000mhz 500mhz 250mhz 125mhz -160.0 -150.0 -140.0 -130.0 -120.0 -110.0 -100.0 -90.0 -80.0 -70.0 -60.0 1.0 10.0 100.0 1000.0 10000.0 100000.0 phase noise (dbc/hz) offset frequency (khz) synthesizer phase noise 4000mhz vco frequency, 52mhz crystal oscillator 2000mhz 1000mhz 500mhz 250mhz 125mhz -160.0 -150.0 -140.0 -130.0 -120.0 -110.0 -100.0 -90.0 -80.0 -70.0 -60.0 1.0 10.0 100.0 1000.0 10000.0 100000.0 phase noise (dbc/hz) offset frequency (khz) synthesizer phase noise 5200mhz vco frequency, 26mhz crystal oscillator 2600mhz 1300mhz 650mhz 325mhz 162.5mhz -160.0 -150.0 -140.0 -130.0 -120.0 -110.0 -100.0 -90.0 -80.0 -70.0 -60.0 1.0 10.0 100.0 1000.0 10000.0 100000.0 phase noise (dbc/hz) offset frequency (khz) synthesizer phase noise 5200mhz vco frequency, 52mhz crystal oscillator 2600mhz 1300mhz 650mhz 325mhz 162.5mhz 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.0 500.0 1000.0 1500.0 2000.0 2500.0 3000.0 rms integrated phase noise () lo frequency (mhz) synthesizer rms integrated phase noise integration bandwidth 1khz to 40mhz 26mhz tcxo 52mhz tcxo note: ? 26mhz crystal oscillator: ndk ena3523a ? 52mhz crystal oscillator: ndk ena3560a
15 of 23 rffc2071/2072 ds100920 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . typical vco performance characteristics v dd =+3v and ta=+27c unless stated. measured on rffc2071/rffc2072 evaluation board. 1200 1300 1400 1500 1600 1700 1800 0 20406080100120 vco frequency (mhz) ct_cal word vco1 frequency versus ct_cal vco1 with lo divide by 2 -40 deg c +27 deg c +85 deg c 0 5 10 15 20 25 1200 1300 1400 1500 1600 1700 1800 kvco (mhz/v) vco frequency /2 (mhz) vco1 frequency versus kvco lo divide by 2 vco1 1600 1700 1800 1900 2000 2100 2200 2300 0 20406080100120 vco frequency (mhz) ct_cal word vco2 frequency versus ct_cal vco2 with lo divide by 2 -40 deg c +27 deg c +85 deg c 0 5 10 15 20 25 30 1600 1700 1800 1900 2000 2100 2200 2300 kvco (mhz/v) vco frequency /2 (mhz) vco2 frequency versus kvco lo divide by 2 vco2 2100 2200 2300 2400 2500 2600 2700 2800 2900 0 20406080100120 vco frequency (mhz) ct_cal word vco3 frequency versus ct_cal vco3 with lo divide by 2 -40 deg c +27 deg c +85 deg c 0 5 10 15 20 25 30 2200 2300 2400 2500 2600 2700 2800 2900 kvco (mhz/v) vco frequency /2 (mhz) vco3 frequency versus kvco lo divide by 2 vco3
16 of 23 rffc2071/2072 ds100920 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . typical vco performance characteristics v dd =+3v and ta=+27c unless stated. measured on rffc2071/rffc2072 evaluation board. 1475 1480 1485 1490 1495 1500 1505 0.00.51.01.5 vco1 frequency /2 (mhz) tuning voltage (volts) vco1 frequency versus tuning voltage for the same coarse tune setting, lo divide by two -40 deg c +27 deg c +85 deg c 2465 2470 2475 2480 2485 2490 2495 2500 2505 2510 2515 0.0 0.5 1.0 1.5 vco3 frequency /2 (mhz) tuning voltage (volts) vco3 frequency versus tuning voltage for the same coarse tune setting, lo divide by two -40 deg c +27 deg c +85 deg c 1980 1985 1990 1995 2000 2005 2010 2015 2020 0.0 0.5 1.0 1.5 vco2 frequency /2 (mhz) tuning voltage (volts) vco2 frequency versus tuning voltage for the same coarse tune setting, lo divide by two -40 deg c +27 deg c +85 deg c -160.0 -150.0 -140.0 -130.0 -120.0 -110.0 -100.0 -90.0 -80.0 -70.0 -60.0 10.0 100.0 1000.0 10000.0 100000.0 phase noise (dbc/hz) offset frequency (khz) vco phase noise with lo divide by 2 2500mhz vco3 2000mhz vco2 1500mhz vco1
17 of 23 rffc2071/2072 ds100920 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . typical supply current performance characteristics v dd =+3v and ta=+27c unless stated. 80.0 90.0 100.0 110.0 120.0 130.0 140.0 1234567 current (ma) mixer bias current setting (mix_idd) total supply current versus mixer bias setting one mixer enabled, lo frequency = 1000mhz -40 deg c, +2.7v -40 deg c, +3.0v -40 deg c, +3.3v +27 deg c, +2.7v +27 deg c, +3.0v +27 deg c, +3.3v +85 deg c, +2.7v +85 deg c, +3.0v +85 deg c, +3.3v
18 of 23 rffc2071/2072 ds100920 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . typical rf mixer 2 performance characteristics v dd =+3v and ta=+27c unless stated. measured on rffc2071/rffc2072 evaluation board. 0.0 5.0 10.0 15.0 20.0 25.0 30.0 0.0 5.0 10.0 15.0 20.0 25.0 30.0 500 750 1000 1250 1500 1750 2000 2250 p in 1db (dbm) iip3 (dbm) rf input frequency (mhz) mixer 2 linearity performance mix_idd = 5, +3.0v, if output = 100mhz input ip3 pin 1db
19 of 23 rffc2071/2072 ds100920 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . typical rf mixer 1 performance characteristics v dd =+3v and ta=+27c unless stated. meas ured on rffc2071 evaluation board. 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 500 750 1000 1250 1500 1750 2000 noise figure (db) lo frequency (mhz) mixer 1 noise figure versus frequency if output = 100mhz mix_idd = 1 mix_idd = 2 mix_idd = 3 mix_idd = 4 mix_idd = 5 mix_idd = 6 mix_idd = 7
20 of 23 rffc2071/2072 ds100920 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . typical performance characteristics of both rf mixers v dd =+3v and ta=+27c unless stated. measured on rffc2071 evaluation board. -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 400.0 600.0 800.0 1000.0 1200.0 1400.0 1600.0 level at mixer 1 output (dbm) rf input frequency (mhz) lo & rf leakage at mixer 1 output rf input power 0dbm, mix1_idd = 4 if output at 100mhz lo leakage (high side) rf leakage -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 400.0 600.0 800.0 1000.0 1200.0 1400.0 1600.0 level at mixer 2 output (dbm) rf input frequency (mhz) lo & rf leakage at mixer 2 output rf input power 0dbm, mix2_idd = 4 if output at 100mhz lo leakage (high side) rf leakage -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 200 400 600 800 1000 1200 1400 1600 1800 2000 lo leakage (dbm) lo frequency (mhz) typical lo leakage at mixer output +3.0v supply voltage path 1, -40 deg c path 1, +27 deg c path 1, +85 deg c path 2, -40 deg c path 2, +27 deg c path 2, +85 deg c
21 of 23 rffc2071/2072 ds100920 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . typical full duplex mode performance characteristics v dd =+3v and ta=+27c unless stated. meas ured on rffc2071 evaluation board. 40.0 50.0 60.0 70.0 80.0 90.0 100.0 0 500 1000 1500 2000 2500 isolation (db) rf input frequency (mhz) mixer to mixer isolation in full duplex mode lo = rf input + 100mhz mix_idd = 4 rffc2071 typical operating current in ma. full duplex mode (both mixers enabled) with +3v supply. mix2_idd mix1_idd 1234567 1 121 126 131 136 142 146 151 2 126 131 136 141 147 151 156 3 131 136 141 147 152 156 161 4 136141147152157162167 5 141 146 152 157 162 167 172 6 146 151 156 161 167 171 176 7 151 156 161 166 171 176 181
22 of 23 rffc2071/2072 ds100920 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . package drawing qfn, 32-pin, 5mmx5mm
23 of 23 rffc2071/2072 ds100920 7628 thorndike road, greensboro, nc 27409-9421 for sales or technical support, contact rfmd at (+1) 336-678-5570 or sales-support@rfmd.com . ordering information rffc2071 rffc2072 part number description devices/container rffc2071sb 32-pin qfn 5-piece sample bag rffc2071sq 32-pin qfn 25-piece sample bag rffc2071sr 32-pin qfn 100-piece reel rffc2071tr7 32-pin qfn 750-piece reel rffc2071tr13 32-pin qfn 2500-piece reel dkfc2071 complete design kit 1 box part number description devices/container rffc2072sb 32-pin qfn 5-piece sample bag rffc2072sq 32-pin qfn 25-piece sample bag RFFC2072SR 32-pin qfn 100-piece reel rffc2072tr7 32-pin qfn 750-piece reel rffc2072tr13 32-pin qfn 2500-piece reel dkfc2072 complete design kit 1 box

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